In a random access memory (RAM) which can write and read data at random in and from a memory unit, a plurality of memory cells are arranged into a two-dimensional matrix pattern. Further, data given from the outside are written in the memory cells arranged at intersections between a selected word line and selected bit lines, or read out of the memory cells through sense amplifiers.
In more detail, when data are written in the memory cell, a word line is first selected on the basis of an address signal inputted from the outside, so that the memory cells connected to the word line are selected. Here, the data inputted from the outside are inputted to a pair of bit lines selected by a write circuit and through a common data line pair respectively, and then written in the memory cells.
On the other hand, when data are read, first a word line is selected on the basis of an address signal inputted from the outside, so that the memory cells connected to the word line are selected. After that, the selected memory cells output data stored therein to a pair of the bit lines, respectively. The data outputted to a pair of the bit lines are transmitted to a pair of common bit lines through a column decoder, amplified by sense amplifiers, and then outputted to the outside. Here, a 4-M SRAM will be described hereinbelow as an example of the conventional semiconductor memory devices. FIG. 3 shows a partial circuit diagram showing the same. As shown, a plurality of cells 1(1), 1(2), . . for storing data are connected between a bit line pair composed of a bit line BL and a bit line NBL (an inversion signal line of the bit line BL). The cell 1 is of a static type memory cell as shown in FIG. 6, for instance. These memory cells are arranged into a matrix pattern so as to form a memory cell array. A plurality of the memory cells 1, 1, . . arranged in the same column of the memory cell array are connected between the same two bit lines BL and NBL, and a plurality of the memory cells 1, 1, . . arranged in the same row are connected to any one of word lines WL(1), WL(2), . . . In an example shown in FIG. 3, only one bit line pair and only two word lines WL(1) and WL(2) are shown for brevity. Here, the cell 1(1) can be selected by the word line WL(1). To the bit line pair between which the cell 1(1) is connected, a first column decoder FCD and a second column decoder SCD are connected. A column decode signal CD and CDI (an inversion signal of the column decode signal CD) are given to the first column decoder FCD. Another column decode signal CDP and CDPI (an inversion signal of the column decode signal CDP) are given to the second column decoder SCD. Further, the bit line pair BL and NBL are connected to a data line pair (composed of common data line pair DL and NDL) via both the first column decoder FCD and the second column decoder SCD. Between the two common data line pairs DL and NDL, two write transistors 2 are connected. To the two write transistors 2, a data input line DIN and a data input line DINI (an inversion signal line of the data input line DIN) are connected.
In the semiconductor memory device shown in FIG. 3, the number of input/output bits is 8. Further, a double-word line selection method is adopted as the word line selection method, and 512 main word lines are arranged so as to be selected on the basis of addresses X1 to X9. Further, the memory cell array is divided into 32 sections, and each section is composed of 128 (16.times.8 bit) columns. As shown in FIG. 3, the columns are selected by the first and second column decoders FCD and SCD constructed hierarchically. In more detail, the first column decoder FCD is arranged in units of 4 columns, and the second column decoder SCD is also arranged in unit of 4 columns. Therefore, it is possible to select any one of the 16 columns on the basis of the column decode signals CD, CDI; and CDP, CDPI. As described above, since the columns can be selected hierarchically on the basis of the first and second column decoders FCD and SCD, there exists such an advantage that the number of column decode signals can be reduced so that the sense amplifiers can be arranged easily and further the pattern area can be reduced. For example, in the case of one-stage column decoders, 32 decode signals are necessary. In the case of two-stage column decoders, however, 16 decode signals are enough as far as 16 columns are selected hierarchically. In this case, since the gate capacitance connected to the column decode signal lines can be also reduced, the access time can be also increased.
Here, the operation of writing data in the cell 1(1) will be described hereinbelow. First, when the word line WL(1) is selected, the cell 1(1) connected to the selected word line WL(1) is selected. Further, one of the 16 columns is selected on the basis of the column decode signals CD and CDI applied to the first column decoder FCD and the column decode signals CDP and CDPI applied to the second column decoder SCD. A pair of data to be written which are formed according to the write data inputted from the outside and inputted to the data input lines DIN and DINI are at a high potential on one side and at a low potential on the other side, respectively, as shown in FIG. 4(A). Here, when a logical product of a section decode signal SD and a write signal WE is given, the two write transistors 2 are selected. On the basis of the data on the data input lines DIN and DINI, the selected write transistors 2 give the high potential and the low potential to the common data line pair DL and NDL, respectively. The data on the common data line pair DL and NDL are given to the bit line pair BL and. NBL via the first and second column decoders, respectively. Once the data are given to the bit line pair BL and NBL as described above, data is to be written to the cell 1(1) selected by the word line WL(1).
On the other hand, the data read process is quite the same as above. The cell 1(1) is selected; the bit line pair BL and NBL are selected; data is given to the common data line pair DL and NDL from the cell 1(1); and then the data is read out via sense amplifiers (not shown).
Here, when the data write operation is taken into account, the data on the data input lines DIN and DINI are transmitted to one of the bit lines BL and NBL via the two write transistors 2 and the turned-on column decoder FCD or SCD, and then given to the cell 1. In the conventional memory device, however, since there exist turn-on resistances of the write transistors 2 and the first or second column decoder FCD or SCD, the low-side potential of the bit line pair BL and NBL rises considerably high, as compared with the low-side potential of the data input line pair DIN and DINI. In other words, as shown in FIG. 4(B), the low-side potential of the data transmitted to the bit lines BL and NBL becomes higher by .DELTA.VI than the low-side potential of the data given to the data input lines DIN and DINI.
Therefore, once the low potential of the bit line pair increases, since the cell 1 is not symmetrical with respect to the bit line pair due to the influence of the parasitic resistance thereof, there arises a problem in that data is not written in the cell properly and reliably.
As described above, in the conventional semiconductor memory device provided with the column decoders of more than two stages, since the low-side potential rises due to the turn-on resistance of the column decoder transistor, there exists a drawback in that the data cannot be written in the cell 1 properly, with the result that not only the access speed deteriorates but also the reliability is degraded.
In addition, in the conventional semiconductor memory device, since the number of bits (e.g., 8 bits) is the same on both the input (write) and output (read) sides, it is difficult to design such a semiconductor memory device that the number of input bits is different from that of the output bits (in particular when the number of input bits is larger than that of the output bits), so that the degree of design freedom is low when the access speed is required to be improved.